package SimpleLACore

import chisel3._
import chisel3.util._

trait SimpleLACoreParam {
  def IPEEnable = false
  def initPC = 0x1c000000L.U(32.W)
  def nTLB = 16
  def lgnTLB = log2Ceil(nTLB)
  def TimerBits = 32
  def nWays: Int = 2
  def nSets: Int = 16
  def lineWords: Int = 4
  def lgnWays: Int = log2Ceil(nWays)
  def idxBits: Int = log2Ceil(nSets)
  def lgLineWords: Int = log2Ceil(lineWords)
  def lgLineBytes: Int = lgLineWords + 2
  def tagBits: Int = 32 - lgLineBytes - idxBits
  def set0whenNE: Boolean = true
}
